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  • Ho Chi Minh university of technology(HCMUT)
  • Ho Chi Minh City

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  1. RISCV-RV32IM-CPU RISCV-RV32IM-CPU Public

    Verilog implementation of a 5-stage pipelined RISC-V RV32IM CPU featuring Dynamic Branch Prediction, Caches, and Hardware Multiplication/Division

    Verilog 2

  2. UART-IP-CORE UART-IP-CORE Public

    A configurable, full-duplex UART IP Core in Verilog featuring AXI4-Lite interface and Asynchronous FIFOs for robust SoC integration.

    Verilog 1

  3. MIPS-Processor MIPS-Processor Public

    5-stage pipelined 32-bit MIPS microprocessor and cache in Verilog

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  4. HCMUT-LAB-DSA HCMUT-LAB-DSA Public

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  5. MCU-LAB1 MCU-LAB1 Public

    LAB1-MCU-2025

  6. MCU-LAB2 MCU-LAB2 Public

    LAB2-MCU-2025

    C