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Ho Chi Minh university of technology(HCMUT)
- Ho Chi Minh City
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RISCV-RV32IM-CPU
RISCV-RV32IM-CPU PublicVerilog implementation of a 5-stage pipelined RISC-V RV32IM CPU featuring Dynamic Branch Prediction, Caches, and Hardware Multiplication/Division
Verilog 2
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UART-IP-CORE
UART-IP-CORE PublicA configurable, full-duplex UART IP Core in Verilog featuring AXI4-Lite interface and Asynchronous FIFOs for robust SoC integration.
Verilog 1
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MIPS-Processor
MIPS-Processor Public5-stage pipelined 32-bit MIPS microprocessor and cache in Verilog
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