add DFLL closed loop support in addition to crystalless configuration options#389
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hathach wants to merge 1 commit into
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add DFLL closed loop support in addition to crystalless configuration options#389hathach wants to merge 1 commit into
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Pull request overview
This PR updates SAMD51 startup clock initialization to restore closed-loop DFLL operation for crystal-based boards while preserving the existing USB clock recovery/open-loop behavior for CRYSTALLESS builds, addressing issue #386.
Changes:
- Splits SAMD51 DFLL configuration into
CRYSTALLESSand crystal-backed paths. - Adds DFLL reference clock routing through GCLK3 for non-crystalless boards.
- Configures closed-loop DFLL multiplication against the 32.768 kHz crystal reference.
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| while ( (OSCCTRL->STATUS.reg & (OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC)) | ||
| != (OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC) ) | ||
| { | ||
| /* Wait for synchronization and coarse lock */ |
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fix #386